Renesas H8/3067 Series User Manual page 948

Appendix D Pin States
Modes 6 and 7: Figure D.4 is a timing diagram for the case in which RES goes low during an
operation in mode 6 or 7. As soon as RES goes low, all ports are initialized to the input state.
/φ goes to the output state at the next rise of φ after RES goes low.
Clock pin P6
7
P6 /φ
7
RES
Internal reset
signal
I/O port
Figure D.4 Reset during Operation (Modes 6 and 7)
Rev. 4.00 Jan 26, 2006 page 924 of 938
REJ09B0276-0400
High impedance