Renesas H8/3067 Series User Manual page 197

When an access is made to DRAM space designated as an 8-bit-access area in ABWCR, only
UCAS is output. When the entire DRAM space is designated as 8-bit-access space and CSEL = 0,
PB5 can be used as an input/output port.
Note that RAS down mode cannot be used when a device other than DRAM is connected to
external space and HWR and LWR are used as write strobes. In this case, also, an idle cycle (Ti) is
always inserted when an external access to other than DRAM space occurs after a DRAM space
access. For details, see section 6.9, Idle Cycle.
CSEL Settings and UCAS
Table 6.8
UCAS UCAS UCAS UCAS
CSEL
0 PB4
HWR
1
Figure 6.21 shows the control timing.
A
CSn (RAS)
PB
4
Byte control
PB
RD(WE)
Note: n = 2 to 5
Figure 6.21 Control Timing (Upper-Byte Write Access When CSEL = 0)
UCAS and LCAS
UCAS UCAS
T
p
φ
to A
23 0
(UCAS)
(LCAS)
5
LCAS Output Pins
LCAS LCAS
LCAS LCAS LCAS LCAS
PB5
LWR
Tr
Row Column
Rev. 4.00 Jan 26, 2006 page 173 of 938
Section 6 Bus Controller
T T
c1 c2
REJ09B0276-0400