Table of Contents
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Section 1 Overview
Table 1.1
Features
Feature
Description
CPU
Upward-compatible with the H8/300 CPU at the object-code level
General-register machine
•
High-speed operation
•
•
•
16-Mbyte address space
Instruction features
•
•
•
•
•
Memory
H8/3067
•
•
H8/3066
•
•
H8/3065
•
•
•
Interrupt
•
controller
•
Rev. 4.00 Jan 26, 2006 page 2 of 938
REJ09B0276-0400
Sixteen 16-bit general registers
(also usable as sixteen 8-bit registers or eight 32-bit registers)
Maximum clock rate: 20 MHz
Add/subtract: 100 ns
Multiply/divide: 700 ns
8/16/32-bit data transfer, arithmetic, and logic instructions
Signed and unsigned multiply instructions (8 bits x 8 bits, 16 bits x 16 bits)
Signed and unsigned divide instructions (16 bits ÷ 8 bits, 32 bits ÷ 16 bits)
Bit accumulator function
Bit manipulation instructions with register-indirect specification of bit positions
ROM: 128 kbytes
RAM: 4 kbytes
ROM: 96 kbytes
RAM: 4 kbytes
ROM: 64 kbytes
RAM: 2 kbytes
Seven external interrupt pins: NMI, IRQ
36 internal interrupts
Three selectable interrupt priority levels
to IRQ
0
5
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