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Bits 2 to 0—Clock Select 2 to 0 (CSK2 to CSK0): These bits select whether the clock input to
TCNT is an internal or external clock.
Three internal clocks can be selected, all divided from the system clock (φ): φ/8, φ/64, and φ/8192.
The rising edge of the selected internal clock triggers the count.
When use of an external clock is selected, three types of count can be selected: at the rising edge,
the falling edge, and both rising and falling edges.
Some functions differ between channels 0 and 2 and channels 1 and 3.
Bit 2
Bit 1
Bit 0
CKS2
CKS1
CKS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Notes: 1. If the clock input of channel 0 is the TCNT1 overflow signal and that of channel 1 is the
TCNT0 compare match signal, no incrementing clock is generated. Do not use this
setting.
2. If the clock input of channel 2 is the TCNT3 overflow signal and that of channel 3 is the
TCNT2 compare match signal, no incrementing clock is generated. Do not use this
setting.
Description
Clock input disabled
Internal clock, counted on rising edge of φ/8
Internal clock, counted on rising edge of φ/64
Internal clock, counted on rising edge of φ/8192
Channel 0: Count on TCNT1 overflow signal *
Channel 1: Count on TCNT0 compare match A *
Channel 2: Count on TCNT3 overflow signal *
Channel 3: Count on TCNT2 compare match A *
External clock, counted on falling edge
External clock, counted on rising edge
External clock, counted on both rising and falling edges
Section 10 8-Bit Timers
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2
Rev. 4.00 Jan 26, 2006 page 407 of 938
(Initial value)
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REJ09B0276-0400
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