Cpu Interface; 16-Bit Accessible Registers - Renesas H8/3067 Series User Manual

9.3

CPU Interface

9.3.1

16-Bit Accessible Registers

The timer counters (TCNTs), general registers A and B (GRAs and GRBs) are 16-bit registers,
and are linked to the CPU by an internal 16-bit data bus. These registers can be written or read a
word at a time, or a byte at a time.
Figures 9.4 and 9.5 show examples of word read/write access to a timer counter (TCNT). Figures
9.6, 9.7, 9.8, and 9.9 show examples of byte read/write access to TCNTH and TCNTL.
On-chip data bus
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CPU L
Figure 9.4 Access to Timer Counter (CPU Writes to TCNT, Word)
On-chip data bus
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CPU L
Figure 9.5 Access to Timer Counter (CPU Reads TCNT, Word)
Bus interface
Bus interface
Section 9 16-Bit Timer
TCNTH TCNTL
TCNTH TCNTL
Rev. 4.00 Jan 26, 2006 page 359 of 938
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data bus
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data bus
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