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Appendix B Internal I/O Registers
TCR0—Timer Control Register
Bit
Initial value
Read/Write
Clock edge 1 and 0
Bit 4
CKEG1
0
0
1
Counter clear 1 and 0
Bit 6
Bit 5
CCLR1
CCLR0
0
0
1
0
1
1
Rev. 4.00 Jan 26, 2006 page 838 of 938
REJ09B0276-0400
7
6
5
CCLR1
CCLR0
1
0
0
R/W
R/W
Timer prescaler 2 to 0
Bit 2
Bit 1
Bit 0
TPSC2
TPSC1
TPSC0
0
0
1
0
0
1
1
0
0
1
1
0
1
1
Bit 3
CKEG0
0
Rising edges counted
1
Falling edges counted
—
Both edges counted
TCNT is not cleared
TCNT is cleared by GRA compare match or input capture
TCNT is cleared by GRB compare match or input capture
Synchronous clear : TCNT is cleared in synchronization with other
synchronized timers
H'FFF68
4
3
2
CKEG1
CKEG0
TPSC2
0
0
0
R/W
R/W
R/W
TCNT Clock Source
Internal clock : φ
Internal clock : φ / 2
Internal clock : φ / 4
Internal clock : φ / 8
External clock A : TCLKA input
External clock B : TCLKB input
External clock C : TCLKC input
External clock D : TCLKD input
Counted Edges of External Clock
TCNT clear Sources
(Initial value)
16-bit timer channel 0
1
0
TPSC1
TPSC0
0
0
R/W
R/W
(Initial value)
(Initial value)
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