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14.3
Operation
14.3.1
Overview
The main features of the smart card interface are as follows.
• One frame consists of 8-bit data plus a parity bit.
• In transmission, a guard time of at least 2 etu (elementary time units: the time for transfer of
one bit) is provided between the end of the parity bit and the start of the next frame.
• If a parity error is detected during reception, a low error signal level is output for a1 etu period
10.5 etu after the start bit.
• If an error signal is detected during transmission, the same data is transmitted automatically
after the elapse of 2 etu or longer.
• Only asynchronous communication is supported; there is no synchronous communication
function.
14.3.2
Pin Connections
Figure 14.2 shows a pin connection diagram for the smart card interface.
In communication with a smart card, since both transmission and reception are carried out on a
single data transmission line, the TxD pin and RxD pin should both be connected to this line. The
data transmission line should be pulled up to V
When the smart card uses the clock generated on the smart card interface, the SCK pin output is
input to the CLK pin of the smart card. If the smart card uses an internal clock, this connection is
unnecessary.
The reset signal should be output from one of the H8/3067 Group's generic ports.
In addition to these pin connections, power and ground connections will normally also be
necessary.
Section 14 Smart Card Interface
with a resistor.
CC
Rev. 4.00 Jan 26, 2006 page 551 of 938
REJ09B0276-0400
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