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Section 21 Electrical Characteristics
φ
t
AD
A
to A
23
0
CS
to CS
5
2
(RAS
to RAS
)
5
2
UCAS, LCAS
(read)
RD (WE)
(read)
D
to D
15
0
(read)
UCAS, LCAS
(write)
RD (WE)
(write)
D
to D
15
0
(write)
RFSH
High
Note: * Specification from the earliest negation timing of RAS and CAS.
Rev. 4.00 Jan 26, 2006 page 746 of 938
REJ09B0276-0400
T
T
p
r
t
AD
t
AS1
t
RP
t
RAD1
High
Figure 21.17 DRAM Bus Timing (Read/Write)
T
C1
t
AD
t
RAH
t
ASD
t
CAS1
t
RAC
t
AA
t
CAC
t
CASD1
t
ASD
t
WCS
t
t
WDD
WDS
T
C2
t
RAD2
t
CASD2
t
CP
t
t
RDS
RDH*
t
CASD2
t
CAS2
t
CP
t
WCD
t
WCH
t
WDH
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