Renesas H8/3067 Series User Manual page 368

Section 9 16-Bit Timer
Bit 1—Input Capture/Compare Match Flag A1 (IMFA1): This status flag indicates GRA1
compare match or input capture events.
Bit 1
IMFA1 Description
0 [Clearing conditions]
Read IMFA1 when IMFA1 =1, then write 0 in IMFA1.
DMAC activated by IMIA1 interrupt.
1 [Setting conditions]
TCNT1 = GRA1 when GRA1 functions as an output compare register.
TCNT1 value is transferred to GRA1 by an input capture signal when GRA1 functions as
an input capture register.
Bit 0—Input Capture/Compare Match Flag A0 (IMFA0): This status flag indicates GRA0
compare match or input capture events.
Bit 0
IMFA0 Description
0 [Clearing conditions]
Read IMFA0 when IMFA0 =1, then write 0 in IMFA0.
DMAC activated by IMIA0 interrupt.
1 [Setting conditions]
TCNT0 = GRA0 when GRA0 functions as an output compare register.
TCNT0 value is transferred to GRA0 by an input capture signal when GRA0 functions as
an input capture register.
Rev. 4.00 Jan 26, 2006 page 344 of 938
REJ09B0276-0400
(Initial value)
(Initial value)