Block Diagram - Renesas H8/3067 Series User Manual

Renesas 16-bit single-chip microcomputer

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Block Diagram

Figure 6.1 shows a block diagram of the bus controller.

Internal address bus

Internal signals

CPU bus request signal

DMAC bus request signal

DRAM interface bus request signal

CPU bus acknowledge signal

DMAC bus acknowledge signal

DRAM interface bus acknowledge signal

: Bus width control register

: Access state control register

: Wait control register H

: Wait control register L

: Bus release control register

: Chip select control register

: DRAM control register A

: DRAM control register B

: Refresh timer control/status register

: Refresh timer counter

: Refresh time constant register

ADRCR* : Address control register

: Bus control register

Note: * This register is provided only in the flash memory R version and mask ROM versions.

control signals

DRAM control

Figure 6.1 Block Diagram of Bus Controller

DRAM interface

Rev. 4.00 Jan 26, 2006 page 121 of 938

Section 6 Bus Controller

Internal signals

Bus mode control signal

Bus size control signal

Access state control signal

Wait request signal

REJ09B0276-0400

H8/3067H8/3066 H8/3065 H8/3067rf