Renesas H8/3067 Series User Manual page 414

Section 9 16-Bit Timer
Contention between Counter Clearing by Input Capture and Counter Increment: If an input
capture signal and counter increment signal occur simultaneously, the counter is cleared according
to the input capture signal. The counter is not incremented by the increment signal.The counter is
not incremented by the increment signal. The value before the counter is cleared is transferred to
the general register. See figure 9.43.
φ
Input capture signal
Counter clear signal
TCNT input clock
TCNT
GR
Figure 9.43 Contention between Counter Clearing by Input Capture and Counter
Rev. 4.00 Jan 26, 2006 page 390 of 938
REJ09B0276-0400
N
Increment
H'0000
N