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Section 10 8-Bit Timers
10.2.5
Timer Control/Status Registers (TCSR)
TCSR0
Bit
7
CMFB
Initial value
0
Read/Write
R/(W)*
TCSR2
Bit
7
CMFB
Initial value
0
Read/Write
R/(W)*
TCSR1, TCSR3
Bit
7
CMFB
Initial value
0
Read/Write
R/(W)*
Note: * Only 0 can be written to bits 7 to 5, to clear these flags.
The timer control/status registers (TCSR0 to TCSR3) are 8-bit registers that indicate compare
match/input capture and overflow statuses, and control compare match output/input capture edge
selection.
Each TCSR is initialized to H'00 by a reset and in standby mode.
Rev. 4.00 Jan 26, 2006 page 408 of 938
REJ09B0276-0400
6
5
CMFA
OVF
ADTE
0
0
R/(W)*
R/(W)*
R/W
6
5
CMFA
OVF
0
0
R/(W)*
R/(W)*
6
5
CMFA
OVF
ICE
0
0
R/(W)*
R/(W)*
R/W
4
3
2
OIS3
OIS2
0
0
0
R/W
R/W
4
3
2
OIS3
OIS2
1
0
0
R/W
R/W
4
3
2
OIS3
OIS2
0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
1
0
OS1
OS0
0
0
R/W
R/W
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