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Contention between General Register Read and Input Capture: If an input capture signal
occurs during the T
state of a general register read cycle, the value before input capture is read.
3
See figure 9.42.
φ
Address bus
Internal read signal
Input capture signal
GR
Internal data bus
Figure 9.42 Contention between General Register Read and Input Capture
General register read cycle
T
T
1
2
GR address
X
X
Rev. 4.00 Jan 26, 2006 page 389 of 938
Section 9 16-Bit Timer
T
3
M
REJ09B0276-0400
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