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6.5.8
Wait Control
In a DRAM access cycle, wait states can be inserted (1) between the T
between the T
state and T
c1
Insertion of T
Wait State between T
rw
by setting the RCW bit to 1 in DRCRB.
Insertion of T
Wait State(s) between T
w
area designated as DRAM space is set to 1, from 0 to 3 wait states can be inserted between the T
state and T
state by means of settings in WCRH and WCRL.
c2
Figure 6.20 shows an example of the timing for wait state insertion.
The settings of the RCW bit in DRCRB and of ASTCR, WCRH, and WCRL do not affect refresh
cycles. Wait states cannot be inserted in a DRAM space access cycle by means of the WAIT pin.
state.
c2
and T
r
c1
and T
c1
: One T
state can be inserted between T
rw
: When the bit in ASTCR corresponding to an
c2
Rev. 4.00 Jan 26, 2006 page 171 of 938
Section 6 Bus Controller
state and T
state, and (2)
r
c1
and T
r
REJ09B0276-0400
c1
c1
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