Renesas H8/3067 Series User Manual page 333

PADDR is initialized to H'00 by a reset and in hardware standby mode in modes 1, 2, 5, 6, and 7.
It is initialized to H'80 by a reset and in hardware standby mode in modes 3 and 4. In software
standby mode it retains its previous setting. Therefore, if a transition is made to software standby
mode while port A is functioning as an input/output port and a PADDR bit is set to 1, the
corresponding pin maintains its output state.
Port A Data Register (PADR): PADR is an 8-bit readable/writable register that stores output
data for port A. When port A functions as an output port, the value of this register is output. When
a bit in PADDR is set to 1, if port A is read the value of the corresponding PADR bit is returned.
When a bit in PADDR is cleared to 0, if port A is read the corresponding pin logic level is read.
Bit 7
PA
Initial value 0
Read/Write R/W
PADR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode it
retains its previous setting.
6 5
PA PA
7 6 5
0 0
R/W R/W
4 3
PA PA
4 3
0 0
R/W R/W
Port A data 7 to 0
These bits store data for port A pins
Rev. 4.00 Jan 26, 2006 page 309 of 938
Section 8 I/O Ports
2 1
PA PA PA
2 1
0 0 0
R/W R/W R/W
REJ09B0276-0400
0
0