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Figure 7.16 shows the timing when the DMAC is activated by the falling edge of DREQ in normal
mode.
T
2
φ
DREQ
Address
bus
RD
HWR
LWR
,
Figure 7.16 Timing of DMAC Activation by Falling Edge of DREQ
CPU cycle
T
T
T
T
T
1
2
1
2
d
Minimum 4 states
DMAC cycle
T
T
T
T
T
1
2
1
2
1
Next sampling point
DREQ in Normal Mode
DREQ
DREQ
Rev. 4.00 Jan 26, 2006 page 253 of 938
Section 7 DMA Controller
CPU
cycle
DMAC cycle
T
T
T
T
2
d
1
2
REJ09B0276-0400
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