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Appendix B Internal I/O Registers
DRCRA—DRAM Control Register A
Bit
Initial value
Read/Write
Rev. 4.00 Jan 26, 2006 page 808 of 938
REJ09B0276-0400
7
6
5
DRAS2
DRAS1
DRAS0
0
0
0
R/W
R/W
R/W
Refresh pin enable
0
1
Self-refresh mode
DRAM self-refreshing is disabled in
0
software standby mode
1
DRAM self-refreshing is enabled
in software standby mode
RAS down mode
0
DRAM interface: RAS up mode selected
1
DRAM interface: RAS down mode selected
Burst access enable
0
Burst disabled (always full access)
DRAM space access performed in fast page mode
1
DRAM area select
DRAS2 DRAS1 DRAS0
0
0
0
1
1
0
1
1
0
0
1
1
0
1
Note: * A single CSn pin serves as a common RAS output pin for a number of
areas. Unused CSn pins can be used as input/output ports.
H'EE026
4
3
2
BE
RDM
SRFMD
1
0
0
R/W
R/W
RFSH pin refresh signal output is disabled
RFSH pin refresh signal output is enabled
Area 5
Area 4
Normal
Normal
Normal
Normal
Normal
Normal
DRAM space
Normal
Normal
Normal
DRAM space
DRAM space
(CS
)
4
DRAM space
DRAM space
DRAM space
(CS
)
(CS
)
5
4
DRAM space(CS
)*
4
DRAM space(CS
DRAM interface
1
0
RFSHE
0
0
R/W
R/W
Area 3
Area 2
Normal
Normal
Normal
DRAM space
(CS
)
2
DRAM space
(CS
)
(CS
)
3
2
DRAM space(CS
)*
2
DRAM space
(CS
(CS
)
3)
2
DRAM space
(CS
)
(CS
)
3
2
DRAM space(CS
)*
2
)*
2
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