Bus Timing - Renesas H8/3067 Series User Manual

φ
NMI
IRQ
E
IRQ
L
IRQ : Edge-sensitive IRQ
E
IRQ : Level-sensitive IRQ (i = 0 to 5)
L
NMI
IRQ
j
(j = 0 to 5)
21.3.3

Bus Timing

Bus timing is shown as follows:
• Basic bus cycle: two-state access
Figure 21.11 shows the timing of the external two-state access cycle.
• Basic bus cycle: three-state access
Figure 21.12 shows the timing of the external three-state access cycle.
• Basic bus cycle: three-state access with one wait state
Figure 21.13 shows the timing of the external three-state access cycle with one wait state
inserted.
• Burst ROM access timing: burst cycle two-state
Figure 21.14 shows the timing of the burst cycle two-state access.
• Burst ROM access timing: burst cycle three-state
Figure 21.15 shows the timing of the burst cycle three-state access.
• Bus-release mode timing
Figure 21.16 shows the bus-release mode timing.
t t
NMIS NMIH
t t
NMIS NMIH
t
NMIS
i
i
t
NMIW
Figure 21.10 Interrupt Input Timing
Section 21 Electrical Characteristics
Rev. 4.00 Jan 26, 2006 page 739 of 938
REJ09B0276-0400