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7.1
Overview
The H8/3067 Group has an on-chip DMA controller (DMAC) that can transfer data on up to four
channels.
When the DMA controller is not used, it can be independently halted to conserve power. For
details see section 20.6, Module Standby Function.
7.1.1
Features
DMAC features are listed below.
• Selection of short address mode or full address mode
Short address mode
8-bit source address and 24-bit destination address, or vice versa
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Full address mode
24-bit source and destination addresses
Maximum two channels available
Selection of normal mode or block transfer mode
• Directly addressable 16-Mbyte address space
• Selection of byte or word transfer
• Activation by internal interrupts, external requests, or auto-request (depending on transfer
mode)
16-bit timer compare match/input capture interrupts (×3)
Serial communication interface (SCI channel 0) transmit-data-empty/receive-data-full
interrupts
External requests
Auto-request
A/D converter conversion-end interrupt
Section 7 DMA Controller
Section 7 DMA Controller
Rev. 4.00 Jan 26, 2006 page 209 of 938
REJ09B0276-0400
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