Table of Contents
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6.2.10 Refresh Timer Counter (RTCNT)........................................................................ 141
6.2.11 Refresh Time Constant Register (RTCOR) ......................................................... 142
(Provided Only in Flash Memory R Version and Mask ROM Versions) ............ 143
6.3
Operation .......................................................................................................................... 144
6.3.1
Area Division ....................................................................................................... 144
6.3.2
Bus Specifications................................................................................................ 147
6.3.3
Memory Interfaces ............................................................................................... 148
6.3.4
Chip Select Signals .............................................................................................. 148
6.3.5
Address Output Method....................................................................................... 150
6.4
Basic Bus Interface ........................................................................................................... 152
6.4.1
Overview.............................................................................................................. 152
6.4.2
Data Size and Data Alignment............................................................................. 152
6.4.3
Valid Strobes........................................................................................................ 153
6.4.4
Memory Areas ..................................................................................................... 154
6.4.5
Basic Bus Control Signal Timing ........................................................................ 156
6.4.6
Wait Control ........................................................................................................ 163
6.5
DRAM Interface ............................................................................................................... 165
6.5.1
Overview.............................................................................................................. 165
DRAM Space and RAS Output Pin Settings ....................................................... 165
6.5.2
6.5.3
Address Multiplexing........................................................................................... 167
6.5.4
Data Bus............................................................................................................... 167
6.5.5
Pins Used for DRAM Interface............................................................................ 168
6.5.6
Basic Timing........................................................................................................ 168
6.5.7
Precharge State Control ....................................................................................... 170
6.5.8
Wait Control ........................................................................................................ 171
Byte Access Control and CAS Output Pin........................................................... 172
6.5.9
6.5.10 Burst Operation.................................................................................................... 174
6.5.11 Refresh Control.................................................................................................... 180
6.5.12 Examples of Use .................................................................................................. 184
6.5.13 Usage Notes ......................................................................................................... 188
6.6
Interval Timer ................................................................................................................... 191
6.6.1
Operation ............................................................................................................. 191
6.7
Interrupt Sources............................................................................................................... 197
6.8
Burst ROM Interface......................................................................................................... 197
6.8.1
Overview.............................................................................................................. 197
6.8.2
Basic Timing........................................................................................................ 197
6.8.3
Wait Control ........................................................................................................ 198
6.9
Idle Cycle .......................................................................................................................... 199
6.9.1
Operation ............................................................................................................. 199
6.9.2
Pin States in Idle Cycle ........................................................................................ 202
Rev. 4.00 Jan 26, 2006 page x of xxii
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