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TISRA—Timer Interrupt Status Register A
Bit:
Initial value:
Read/Write:
Input capture/compare match flag A2
Input capture/compare match interrupt enable A0
0
IMIA0 interrupt requested by IMFA0 flag is disabled
1
IMIA0 interrupt requested by IMFA0 is enabled
Input capture/compare match interrupt enable A1
0
IMIA1 interrupt requested by IMFA1 flag is disabled
1
IMIA1 interrupt requested by IMFA1 is enabled
Input capture/compare match interrupt enable A2
0
IMIA2 interrupt requested by IMFA2 flag is disabled
1
IMIA2 interrupt requested by IMFA2 is enabled
Note: * Only 0 can be written, to clear the flag.
7
6
5
IMIEA2
IMIEA1
1
0
0
R/W
R/W
Input capture/compare match flag A0
[Clearing conditions]
Read IMFA0 when IMFA0=1, then write 0 in IMFA0
0
DMAC activated by IMIA0 interrupt.
[Setting conditions]
TCNT0=GRA0 when GRA0 functions as an output compare register.
1
TCNT0 value is transferred to GRA0 by an input capture signal when GRA0
functions as an input capture register.
Input capture/compare match flag A1
[Clearing conditions]
Read IMFA1 when IMFA1=1, then write 0 in IMFA1
0
DMAC activated by IMIA1 interrupt.
[Setting conditions]
TCNT1=GRA1 when GRA1 functions as an output compare register.
1
TCNT1 value is transferred to GRA1 by an input capture signal when GRA1
functions as an input capture register.
[Clearing conditions]
Read IMFA2 when IMFA2=1, then write 0 in IMFA2
0
DMAC activated by IMIA2 interrupt.
[Setting conditions]
TCNT2=GRA2 when GRA2 functions as an output compare register.
1
TCNT2 value is transferred to GRA2 by an input capture signal when GRA2
functions as an input capture register.
Appendix B Internal I/O Registers
H'FFF64
4
3
2
1
IMIEA0
IMFA2
IMFA1
0
1
0
0
R/W
R/(W)*
R/(W)*
(Initial value)
(Initial value)
(Initial value)
Rev. 4.00 Jan 26, 2006 page 835 of 938
16-bit timer (all channels)
0
IMFA0
0
R/(W)*
(Initial value)
(Initial value)
(Initial value)
REJ09B0276-0400
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