Renesas H8/3067 Series User Manual page 27

Feature Description
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Bus controller
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DMA controller Short address mode
(DMAC)
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Full address mode
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16-bit timer,
3 channels
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Address space can be partitioned into eight areas, with independent bus
specifications in each area
Chip select output available for areas 0 to 7
8-bit access or 16-bit access selectable for each area
Two-state or three-state access selectable for each area
Selection of two wait modes
Number of program wait states selectable for each area
Direct connection of burst ROM
Direct connection of up to 8-Mbyte DRAM (or DRAM interface can be used
as interval timer)
Bus arbitration function
Maximum four channels available
Selection of I/O mode, idle mode, or repeat mode
Can be activated by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, conversion-end interrupts from the A/D converter,
transmit-data-empty and receive-data-full interrupts from the SCI, or external
requests
Maximum two channels available
Selection of normal mode or block transfer mode
Can be activated by compare match/input capture A interrupts from 16-bit
timer channels 0 to 2, conversion-end interrupts from the A/D converter,
external requests, or auto-request
Three 16-bit timer channels, capable of processing up to six pulse outputs or
six pulse inputs
16-bit timer counter (channels 0 to 2)
Two multiplexed output compare/input capture pins (channels 0 to 2)
Operation can be synchronized (channels 0 to 2)
PWM mode available (channels 0 to 2)
Phase counting mode available (channel 2)
DMAC can be activated by compare match/input capture A interrupts
(channels 0 to 2)
Section 1 Overview
Rev. 4.00 Jan 26, 2006 page 3 of 938
REJ09B0276-0400