Operation - Renesas H8/3067 Series User Manual

Section 17 RAM
17.3

Operation

When the RAME bit is set to 1, the on-chip RAM is enabled. Accesses to addresses H'FEF20 to
H'FFF1F in the H8/3067 and H8/3066 in modes 1, 2, and 7, and to addresses H'FFEF20 to
H'FFFF1F in the H8/3067 and H8/3066 in modes 3, 4, and 5, and to addresses H'EF20 to H'FF1F
in mode 6, are directed to the on-chip RAM. In the H8/3065, accesses to addresses H'FF720 to
H'FFF1F in modes 1, 2, and 7, to addresses H'FFF720 to H'FFFF1F in modes 3, 4, and 5, and to
addresses H'F720 to H'FF1F in mode 6, are directed to the on-chip RAM. In modes 1 to 5
(expanded modes), when the RAME bit is cleared to 0, the off-chip address space is accessed. In
mode 6, 7 (single-chip mode), when the RAME bit is cleared to 0, the on-chip RAM is not
accessed: read access always results in H'FF data, and write access is ignored.
Since the on-chip RAM is connected to the CPU by an internal 16-bit data bus, it can be written
and read by word access. It can also be written and read by byte access. Byte data is accessed in
two states using the upper 8 bits of the data bus. Word data starting at an even address is accessed
in two states using all 16 bits of the data bus.
Rev. 4.00 Jan 26, 2006 page 605 of 938
REJ09B0276-0400