Table of Contents
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8.12 Port B ................................................................................................................................ 317
8.12.1 Overview.............................................................................................................. 317
8.12.2 Register Descriptions ........................................................................................... 319
9.1
Overview........................................................................................................................... 327
9.1.1
Features................................................................................................................ 327
9.1.2
Block Diagrams ................................................................................................... 330
9.1.3
Input/Output Pins ................................................................................................. 333
9.1.4
Register Configuration......................................................................................... 334
9.2
Register Descriptions ........................................................................................................ 336
9.2.1
Timer Start Register (TSTR)................................................................................ 336
9.2.2
Timer Synchro Register (TSNC) ......................................................................... 337
9.2.3
Timer Mode Register (TMDR) ............................................................................ 339
9.2.4
Timer Interrupt Status Register A (TISRA)......................................................... 342
9.2.5
Timer Interrupt Status Register B (TISRB) ......................................................... 345
9.2.6
Timer Interrupt Status Register C (TISRC) ......................................................... 348
9.2.7
Timer Counters (TCNT) ...................................................................................... 350
9.2.8
General Registers (GRA, GRB)........................................................................... 351
9.2.9
Timer Control Registers (TCR) ........................................................................... 352
9.2.10 Timer I/O Control Register (TIOR) ..................................................................... 354
9.2.11 Timer Output Level Setting Register C (TOLR) ................................................. 356
9.3
CPU Interface.................................................................................................................... 359
9.3.1
16-Bit Accessible Registers ................................................................................. 359
9.3.2
8-Bit Accessible Registers ................................................................................... 361
9.4
Operation .......................................................................................................................... 362
9.4.1
Overview.............................................................................................................. 362
9.4.2
Basic Functions.................................................................................................... 363
9.4.3
Synchronization ................................................................................................... 371
9.4.4
PWM Mode.......................................................................................................... 373
9.4.5
Phase Counting Mode .......................................................................................... 377
9.4.6
Setting Initial Value of 16-Bit Timer Output....................................................... 379
9.5
Interrupts ........................................................................................................................... 380
9.5.1
Setting of Status Flags ......................................................................................... 380
9.5.2
Timing of Clearing of Status Flags ...................................................................... 382
9.5.3
Interrupt Sources and DMA Controller Activation.............................................. 383
9.6
Usage Notes ...................................................................................................................... 384
10.1 Overview........................................................................................................................... 397
10.1.1 Features................................................................................................................ 397
....................................................................................................... 327
..................................................................................................... 397
Rev. 4.00 Jan 26, 2006 page xiii of xxii
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