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Section 6 Bus Controller
6.11
Register and Pin Input Timing
6.11.1
Register Write Timing
ABWCR, ASTCR, WCRH, and WCRL Write Timing: Data written to ABWCR, ASTCR,
WCRH, and WCRL takes effect starting from the next bus cycle. Figure 6.49 shows the timing
when an instruction fetched from area 0 changes area 0 from three-state access to two-state access.
φ
Address bus
DDR and CSCR Write Timing: Data written to DDR or CSCR for the port corresponding to the
CSn pin to switch between CSn output and generic input takes effect starting from the T
the DDR write cycle. Figure 6.50 shows the timing when the CS
input to CS
output.
1
φ
Address bus
CS
Rev. 4.00 Jan 26, 2006 page 206 of 938
REJ09B0276-0400
T
T
T
1
2
3
3-state access to area 0
Figure 6.49 ASTCR Write Timing
1
High-impedance
Figure 6.50 DDR Write Timing
T
T
T
1
2
3
ASTCR address
2-state access to area 0
pin is changed from generic
1
T
T
1
2
P8DDR address
T
T
1
2
3
T
3
state of
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