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Appendix B Internal I/O Registers
TSNC—Timer Synchro Register
Bit
7
Initial value
1
Read/Write
Timer synchronization 2
0
1
Rev. 4.00 Jan 26, 2006 page 832 of 938
REJ09B0276-0400
6
5
1
1
Reserved bits
Timer synchronization 0
0
1
Timer synchronization 1
Channel 1 timer counter (TCNT1) operates
0
independently (TCNT1 presetting/clearing is
unrelated to other channels)
Channel 1 operates synchronously
1
TCNT1 synchronous presetting/synchronous
clearing is possible
Channel 2 timer counter (TCNT2) operates
independently (TCNT2 presetting/clearing is
unrelated to other channels)
Channel 2 operates synchronously
TCNT2 synchronous presetting/synchronous
clearing is possible
H'FFF61
4
3
SYNC2
1
1
R/W
Channel 0 timer counter (TCNT0) operates
independently (TCNT0 presetting/clearing is
unrelated to other channels)
Channel 0 operates synchronously
TCNT0 synchronous presetting/synchronous
clearing is possible
(Initial value)
16-bit timer (all channels)
2
1
0
SYNC1
SYNC0
0
0
0
R/W
R/W
(Initial value)
(Initial value)
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