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Section 12 Watchdog Timer
12.1.2
Block Diagram
Figure 12.1 shows a block diagram of the WDT.
Interrupt signal
(interval timer)
Reset
(internal, external)
Legend
TCNT:
Timer counter
TCSR:
Timer control/status register
RSTCSR:
Reset control/status register
12.1.3
Pin Configuration
Table 12.1 describes the WDT output pin *
Table 12.1 WDT Pin
Name
Abbreviation
RESO
Reset output
Notes: 1. Not present in the flash memory and flash memory R versions.
2. Open-drain output.
Rev. 4.00 Jan 26, 2006 page 462 of 938
REJ09B0276-0400
Overflow
Interrupt
control
RSTCSR
Reset control
Clock
Figure 12.1 WDT Block Diagram
1
.
I/O
Function
Output *
2
External output of the watchdog timer reset signal
TCNT
TCSR
Internal clock sources
φ/2
φ/32
φ/64
φ/128
Clock
φ/256
selector
φ/512
φ/2048
φ/4096
Internal
data bus
Read/
write
control
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