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D.2
Pin States at Reset
Modes 1 and 2: Figure D.1 is a timing diagram for the case in which RES goes low during an
external memory access in mode 1 or 2. As soon as RES goes low, all ports are initialized to the
input state. AS, RD, HWR, LWR, and CS
The address bus is initialized to the low output level 2.5 φ clock cycles after the low level of RES
is sampled. Clock pin P6
P6
/φ
7
RES
Internal reset
signal
A
to A
19
0
CS
0
AS, RD
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
I/O port,
CS
to CS
7
1
Figure D.1 Reset during Memory Access (Modes 1 and 2)
go high, and D
0
/φ goes to the output state at the next rise of φ after RES goes low.
7
Access to external
memory
T1
T2
to D
go to the high-impedance state.
15
0
T3
High impedance
High impedance
Rev. 4.00 Jan 26, 2006 page 921 of 938
Appendix D Pin States
H'00000
REJ09B0276-0400
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