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Section 18 ROM
Error protection is released only by a reset via the RES pin or a WDT reset, or in the hardware
standby mode.
Figure 18.13 shows the flash memory state transition diagram.
Notes: 1. This is the state in which the P or E bit in FLMCR is set to 1. In this state, NMI input is
disabled. For more information, see section 18.6.4, NMI Input Disable Conditions.
2. For a detailed description of the FLER bits setting conditions, see section 18.3.4, Flash
Memory Status Register (FLMSR).
3. Data can be written to FLMCR and EBR. However, when transition to the software
standby mode was made in the error protection state, the registers are initialized.
Rev. 4.00 Jan 26, 2006 page 640 of 938
REJ09B0276-0400
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