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Section 11 Programmable Timing Pattern Controller (TPC)
Different Triggers for TPC Output Groups 0 and 1: If TPC output groups 0 and 1 are triggered
by different compare match events, the address of the upper 4 bits of NDRA (group 1) is H'FFFA5
and the address of the lower 4 bits (group 0) is H'FFFA7. Bits 3 to 0 of address H'FFFA5 and bits
7 to 4 of address H'FFFA7 are reserved bits that cannot be modified and always read 1.
Address H'FFFA5
Bit
7
NDR7
Initial value
0
Read/Write
R/W
Address H'FFFA7
Bit
7
Initial value
1
Read/Write
Rev. 4.00 Jan 26, 2006 page 442 of 938
REJ09B0276-0400
6
5
NDR6
NDR5
0
0
R/W
R/W
Next data 7 to 4
These bits store the next output
data for TPC output group 1
6
5
1
1
Reserved bits
4
3
NDR4
0
1
R/W
Reserved bits
4
3
NDR3
NDR2
1
0
R/W
R/W
Next data 3 to 0
These bits store the next output
data for TPC output group 0
2
1
0
1
1
1
2
1
0
NDR1
NDR0
0
0
0
R/W
R/W
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