Section 21 Electrical Characteristics
φ
A
to A
,
23
0
CS
n
AS
RD (read)
D
to D
15
0
(read)
HWR, LWR
(write)
D
to D
15
0
(write)
WAIT
Figure 21.13 Basic Bus Cycle: Three-State Access with One Wait State
Rev. 4.00 Jan 26, 2006 page 742 of 938
REJ09B0276-0400
T
T
1
2
t
t
WTS
WTH
T
W
t
t
WTS
WTH
T
3