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11.2.9
TPC Output Control Register (TPCR)
TPCR is an 8-bit readable/writable register that selects output trigger signals for TPC outputs on a
group-by-group basis.
Bit
7
G3CMS1
Initial value
1
Read/Write
R/W
Group 3 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 3
(TP
to TP
15
TPCR is initialized to H'FF by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Section 11 Programmable Timing Pattern Controller (TPC)
6
5
G3CMS0
G2CMS1
1
1
R/W
R/W
Group 2 compare
match select 1 and 0
These bits select
)
12
the compare match
event that triggers
TPC output group 2
(TP
to TP
11
8
4
3
G2CMS0
G1CMS1
G1CMS0
1
1
R/W
R/W
Group 1 compare
match select 1 and 0
These bits select
)
the compare match
event that triggers
TPC output group 1
(TP
to TP
)
7
4
Rev. 4.00 Jan 26, 2006 page 447 of 938
2
1
G0CMS1
G0CMS0
1
1
R/W
R/W
R/W
Group 0 compare
match select 1 and 0
These bits select
the compare match
event that triggers
TPC output group 0
(TP
to TP
)
3
0
REJ09B0276-0400
0
1
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