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H8/3067 Group chip
Figure 6.31 Interconnections and Address Map for 2-CAS 16-Mbit DRAMs with × × × × 16-Bit
CS
(RAS
)
2
2
CS
(RAS
)
3
3
PB
(UCAS)
4
PB
(LCAS)
5
RD (WE)
A
-A
10
1
D
-D
15
0
(a) Interconnections (example)
PB
4
(UCAS)
15
H'400000
Area 2
DRAM (No.1)
H'5FFFFE
H'600000
DRAM (No.2)
Area 3
H'7FFFFE
H'800000
Area 4
Normal
H'9FFFFE
H'A00000
Area 5
Normal
H'BFFFFE
(b) Address map
Organization
2-CAS 16-Mbit DRAM
10-bit row address x 10-bit column address
x16-bit organization
RAS
UCAS
LCAS
No.1
WE
A
-A
9
0
D
-D
15
0
OE
RAS
UCAS
LCAS
No.2
WE
A
-A
9
0
D
-D
15
0
OE
PB
5
(LCAS)
8
7
0
CS
(RAS
)
2
2
CS
(RAS
)
3
3
CS
4
CS
5
Rev. 4.00 Jan 26, 2006 page 185 of 938
Section 6 Bus Controller
REJ09B0276-0400
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