Renesas H8/3067 Series User Manual page 944

Appendix D Pin States
7. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is set to 1.
8. When bit CS7E or CS6E, respectively, in CSCR (chip select control register) is cleared
to 0.
9. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 101.
10. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is set
to 1.
11. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 101, and bit CS5E in CSCR (chip select control register) is
cleared to 0.
12. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is 100, 101, or 110.
13. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is set to 1.
14. When the setting of bits DRAS2, DRAS1, and DRAS0 in DRCRA (DRAM control
register A) is other than 100, 101, or 110, and bit CS4E in CSCR (chip select control
register) is cleared to 0.
15. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is cleared to 0.
16. When any of bits DRAS2, DRAS1, or DRAS0 in DRCRA (DRAM control register A) is
set to 1, and bit CSEL in DRCRB (DRAM control register B) is set to 1; or, when bits
DRAS2, DRAS1, and DRAS0 are all cleared to 0.
17. RESO output is a mask ROM version function. A low level is output only in the case of a
reset due to WDT overflow. There is no bus-released state in modes 6 and 7.
Rev. 4.00 Jan 26, 2006 page 920 of 938
REJ09B0276-0400