System Control Register (Syscr); Table 3.2 Settings Of Bits Msd3 To Msd0 - Renesas H8SX/1500 Series Hardware Manual

Bit Bit Name

7

6

5

4

3

2

1

0
Note: Determined by pins MD1 and MD0.
*
Table 3.2 Settings of Bits MSD3 to MSD0
MCU Operating Mode MD1
1
2
3
3.2.2

System Control Register (SYSCR)

SYSCR controls MAC saturation operation and enables/disables the on-chip RAM and the flash
memory control registers.
Bit 15
Bit Name —
Initial Value 1
R/W R
Bit 7
Bit Name FLSHE
Initial Value 0
R/W R/W
Initial Value R/W
0 R
1 R
0 R
1 R
Undefined* R
Undefined* R
Undefined* R
Undefined* R
MD0
0 1
1 0
1 1
14 13
— MACS
1 0
R R/W
6 5
— —
0 0
R/W R/W
Descriptions
Reserved
These are read-only bits and cannot be modified.
MDS3 MDS2
1 1
1 1
0 1
12 11
— —
1 0
R R/W
4 3
— —
0 0
R/W R/W
Rev. 3.00 Mar. 14, 2006 Page 69 of 804
Section 3 MCU Operating Modes
MDCR
MDS1 MDS0
0 1
0 0
0 0
10 9
— — RAME
1 0
R/W R/W
2 1
— —
0 1
R/W R/W
REJ09B0104-0300
8
1
R/W
0
—
1
R/W