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DMAC cycle
(channel 1)
T
1
φ
Address
bus
RD
HWR
,
LWR
Figure 7.19 Timing of Multiple-Channel Operations
7.4.10
External Bus Requests, DRAM Interface, and DMAC
During a DMAC transfer, if the bus right is requested by an external bus request signal (BREQ) or
by the DRAM interface (refresh cycle), the DMAC releases the bus after completing the transfer
of the current byte or word. If there is a transfer request at this point, the DMAC requests the bus
right again. Figure 7.20 shows an example of the timing of insertion of a refresh cycle during a
burst transfer on channel 0.
T
T
1
φ
Address
bus
RD
HWR LWR
,
Figure 7.20 Bus Timing of DRAM Interface, and DMAC
CPU
cycle
T
T
T
T
T
2
1
2
d
DMAC cycle (channel 0)
T
T
T
T
2
1
2
1
2
DMAC cycle
CPU
(channel 0A)
cycle
T
T
T
T
1
2
1
2
1
Refresh
cycle
T
T
T
T
T
1
2
1
2
d
Rev. 4.00 Jan 26, 2006 page 257 of 938
Section 7 DMA Controller
DMAC cycle
(channel 1)
T
T
T
T
T
2
d
1
2
1
DMAC cycle (channel 0)
T
T
T
T
T
1
2
1
2
1
REJ09B0276-0400
T
2
T
2
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