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6.5
DRAM Interface
6.5.1
Overview
The H8/3067 Group is provided with a DRAM interface with functions for DRAM control signal
(RAS, UCAS, LCAS, WE) output, address multiplexing, and refreshing, that direct connection of
DRAM. In the expanded modes, external address space areas 2 to 5 can be designated as DRAM
space accessed via the DRAM interface. A data bus width of 8 or 16 bits can be selected for
DRAM space by means of a setting in ABWCR. When a 16-bit data bus width is selected, CAS is
used for byte access control. In the case of × 16-bit organization DRAM, therefore, the 2-CAS
type can be connected. A fast page mode is supported in addition to the normal read and write
access modes.
DRAM Space and RAS
6.5.2
Designation of areas 2 to 5 as DRAM space, and selection of the RAS output pin for each area
designated as DRAM space, is performed by setting bits in DRCRA. Table 6.5 shows the
correspondence between the settings of bits DRAS2 to DRAS0 and the selected DRAM space and
RAS output pin.
When an arbitrary value has been set in DRAS2 to DRAS0, a write of a different value other than
000 must not be performed.
RAS Output Pin Settings
RAS
RAS
Section 6 Bus Controller
Rev. 4.00 Jan 26, 2006 page 165 of 938
REJ09B0276-0400
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