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Section 7 DMA Controller
Figure 7.17 shows the timing when the DMAC is activated by level-sensitive low DREQ input in
normal mode.
T
2
φ
DREQ
Address
bus
RD
HWR
LWR
,
Figure 7.17 Timing of DMAC Activation by Low DREQ
Rev. 4.00 Jan 26, 2006 page 254 of 938
REJ09B0276-0400
CPU cycle
T
T
T
T
T
1
2
1
2
d
Minimum 4 states
DMAC cycle
T
T
T
T
T
1
2
1
2
1
Next sampling point
DREQ Level in Normal Mode
DREQ
DREQ
CPU cycle
T
T
T
T
2
1
2
1
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