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BCR—Bus Control Register
7
Bit
ICIS1
ICIS0
Initial value
1
Read/Write
R/W
Idle cycle insertion 0
0
No idle cycle is inserted in case of consecutive external read and write cycles
Idle cycle is inserted in case of consecutive external read and write cycles
1
Idle cycle insertion 1
0
No idle cycle is inserted in case of consecutive external read cycles for different areas
1
Idle cycle is inserted in case of consecutive external read cycles for different areas
6
5
4
BROME
BRSTS1
1
0
0
R/W
R/W
R/W
Burst cycle select 1
Burst access cycle comprises 2 states
0
1
Burst access cycle comprises 3 states
Burst ROM enable
0
Area 0 is a basic bus interface area
1
Area 0 is a burst ROM interface area
Appendix B Internal I/O Registers
H'EE024
3
2
1
BRSTS0
RDEA
0
1
1
R/W
R/W
Area division unit select
0
Area divisions are as follows:
Area 0: 2 MB
Area 1: 2 MB
Area 2: 8 MB
Area 3: 2 MB
Areas 0 to 7 are the same size
1
(2 MB)
Burst cycle select 0
0
Max. 4 words in burst access
Max. 8 words in burst access
1
Rev. 4.00 Jan 26, 2006 page 807 of 938
Bus controller
0
WAITE
0
R/W
Wait pin enable
WAIT pin wait input is disabled
0
WAIT pin wait input is enabled
1
Area 4: 1.93 MB
Area 5: 4 kB
Area 6: 23.75 kB
Area 7: 22 B
REJ09B0276-0400
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