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Section 6 Bus Controller
6.5.11
Refresh Control
The H8/3067 Group is provided with a CAS-before-RAS (CBR) function and self-refresh function
as DRAM refresh control functions.
CAS-Before-RAS (CBR) Refreshing: To select CBR refreshing, set the RCYCE bit to 1 in
DRCRB.
With CBR refreshing, RTCNT counts up using the input clock selected by bits CKS2 to CKS0 in
RTMCSR, and a refresh request is generated when the count matches the value set in RTCOR
(compare match). At the same time, RTCNT is reset and starts counting up again from H'00.
Refreshing is thus repeated at fixed intervals determined by RTCOR and bits CKS2 to CKS0. A
refresh cycle is executed after this refresh request has been accepted and the DRAM interface has
acquired the bus. Set a value in bits CKS2 to CKS0 in RTCOR that will meet the refresh interval
specification for the DRAM used. When RAS down mode is used, set the refresh interval so that
the maximum RAS pulse width specification is met.
RTCNT starts counting up when bits CKS2 to CKS0 are set. RTCNT and RTCOR settings should
therefore be completed before setting bits CKS2 to CKS0.
Also note that a repeat refresh request generated during a bus request, or a refresh request during
refresh cycle execution, will be ignored.
RTCNT operation is shown in figure 6.26, compare match timing in figure 6.27, and CBR refresh
timing in figures 6.28 and 6.29.
RTCOR
H'00
Refresh request
Rev. 4.00 Jan 26, 2006 page 180 of 938
REJ09B0276-0400
RTCNT
Figure 6.26 RTCNT Operation
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