Renesas H8/3067 Series User Manual page 492

Section 12 Watchdog Timer
Bit 7—Watchdog Timer Reset (WRST): During watchdog timer operation, this bit indicates that
TCNT has overflowed and generated a reset signal. This reset signal resets the entire H8/3067 chip
internally. If bit RSTOE is set to 1, this reset signal is also output (low) at the RESO pin to
initialize external system devices. Note that there is no RESO pin in the flash memory and flash
memory R versions.
Bit 7
WRST Description
0 [Clearing condition]
Reset signal at RES pin.
Read WRST when WRST =1, then write 0 in WRST.
1 [Setting condition]
Set when TCNT overflow generates a reset signal during watchdog timer operation
Bit 6—Reset Output Enable (RSTOE): Enables or disables external output at the RESO pin of
the reset signal generated if TCNT overflows during watchdog timer operation. Note that there is
no RESO pin in the flash memory and flash memory R versions.
Bit 6
RSTOE Description
0 Reset signal is not output externally (Initial value)
1 Reset signal is output externally
Bits 5 to 0—Reserved: These bits cannot be modified and are always read as 1.
Rev. 4.00 Jan 26, 2006 page 468 of 938
REJ09B0276-0400
(Initial value)
(Initial value)