Renesas H8/3067 Series User Manual page 157

Bit 4—Burst Cycle Select 1 (BRSTS1): Selects the number of burst cycle states for the burst
ROM interface.
Bit 4
BRSTS1 Description
0 Burst access cycle comprises 2 states
1 Burst access cycle comprises 3 states
Bit 3—Burst Cycle Select 0 (BRSTS0): Selects the number of words that can be accessed in a
burst ROM interface burst access.
Bit 3
BRSTS0 Description
0 Max. 4 words in burst access (burst access on match of address bits above A3)(
1 Max. 8 words in burst access (burst access on match of address bits above A4)
Bit 2—Reserved: Read-only bit, always read as 1.
Bit 1—Area Division Unit Select (RDEA): Selects the memory map area division units. This bit
is valid in modes 3, 4, and 5, and is invalid in modes 1, 2, 6, and 7.
Bit 1
RDEA Description
0 Area divisions are as follows:
1 Areas 0 to 7 are the same size (2 MB)
Bit 0—WAIT Pin Enable (WAITE): Enables or disables wait insertion by means of the WAIT
pin.
Bit 0
WAITE Description
WAIT pin wait input is disabled, and the WAIT pin can be used as an
0
input/output port
WAIT pin wait input is enabled
1
Area 0: 2 MB
Area 1: 2 MB
Area 2: 8 MB
Area 3: 2 MB
Rev. 4.00 Jan 26, 2006 page 133 of 938
Section 6 Bus Controller
(Initial value)
Area 4: 1.93 MB
Area 5: 4 kB
Area 6: 23.75 kB
Area 7: 22 B
(Initial value)
(Initial value)
REJ09B0276-0400