Renesas H8/3067 Series User Manual page 814

Appendix B Internal I/O Registers
Data
Address Register Bus
(Low) Name Width Bit 7
H'FFFE0 ADDRAH 8
H'FFFE1 ADDRAL 8
H'FFFE2 ADDRBH 8
H'FFFE3 ADDRBL 8
H'FFFE4 ADDRCH 8
H'FFFE5 ADDRCL 8
H'FFFE6 ADDRDH 8
H'FFFE7 ADDRDL 8
H'FFFE8 ADCSR 8
H'FFFE9 ADCR 8
Notes: 1. The ADRCR register is provided only in the flash memory R version and mask ROM
versions; it is not present in the flash memory version.
2. The FLMCR and EBR registers are used only in the flash memory and flash memory R
versions, and are not provided in the mask ROM versions.
3. The RAMCR and FLMCR registers are used only in the flash memory and flash
memory R versions, and are not provided in the mask ROM versions.
4. For write access to TCSR, TCNT, and RSTCSR, see section 12.2.4, Notes on Register
Access.
5. The address depends on the output trigger setting.
Legend
WDT: Watchdog timer
TPC: Programmable timing pattern controller
SCI: Serial communication interface
Rev. 4.00 Jan 26, 2006 page 790 of 938
REJ09B0276-0400
Bit Names
Bit 6 Bit 5
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
AD9 AD8 AD7
AD1 AD0 —
ADF ADIE ADST
TRGE — —
Bit 4 Bit 3 Bit 2
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
AD6 AD5 AD4
— — —
SCAN CKS CH2
— — —
Module
Name
Bit 1 Bit 0
AD3 AD2 A/D converter
— —
AD3 AD2
— —
AD3 AD2
— —
AD3 AD2
— —
CH1 CH0
— —