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Section 9 16-Bit Timer
9.6
Usage Notes
This section describes contention and other matters requiring special attention during 16-bit timer
operations.
Contention between TCNT Write and Clear: If a counter clear signal occurs in the T
TCNT write cycle, clearing of the counter takes priority and the write is not performed. See
figure 9.37.
φ
Address bus
Internal write signal
Counter clear signal
TCNT
Figure 9.37 Contention between TCNT Write and Clear
Rev. 4.00 Jan 26, 2006 page 384 of 938
REJ09B0276-0400
TCNT write cycle
T
T
1
2
TCNT address
N
state of a
3
T
3
H'0000
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