Renesas H8/3067 Series User Manual page 218

Section 6 Bus Controller
Contention between RTCOR Write and Compare Match: If a compare match occurs in the T
state of an RTCOR write cycle, writing takes priority and the compare match signal is inhibited.
See Figure 6.41.
Address bus
Internal write signal
RTCNT
RTCOR
Compare match signal
Figure 6.41 Contention between RTCOR Write and Compare Match
RTCNT Operation at Internal Clock Source Switchover: Switching internal clock sources may
cause RTCNT to increment, depending on the switchover timing. Table 6.10 shows the relation
between the time of the switchover (by writing to bits CKS2 to CKS0) and the operation of
RTCNT.
The RTCNT input clock is generated from the internal clock source by detecting the falling edge
of the internal clock. If a switchover is made from a high clock source to a low clock source, as in
case No. 3 in table 6.10, the switchover will be regarded as a falling edge, an RTCNT clock pulse
will be generated, and RTCNT will be incremented.
Rev. 4.00 Jan 26, 2006 page 194 of 938
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T
φ
T T
1 2
RTCOR address
N
N
RTCOR write data
3
N+1
M
Inhibited
3