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Section 9 16-Bit Timer
9.2.6
Timer Interrupt Status Register C (TISRC)
TISRC is an 8-bit readable/writable register that indicates TCNT overflow or underflow and
enables or disables overflow interrupt requests.
Bit
7
Initial value
1
Read/Write
Reserved bit
Note: * Only 0 can be written, to clear the flag.
TISRC is initialized to H'88 by a reset and in standby mode.
Bit 7—Reserved: This bit cannot be modified and is always read as 1.
Bit 6—Overflow Interrupt Enable 2 (OVIE2): Enables or disables the interrupt requested by the
OVF2 flag when OVF2 is set to 1.
Bit 6
OVIE2
Description
0
OVI2 interrupt requested by OVF2 flag is disabled
1
OVI2 interrupt requested by OVF2 flag is enabled
Rev. 4.00 Jan 26, 2006 page 348 of 938
REJ09B0276-0400
6
5
4
OVIE2
OVIE1
OVIE0
0
0
0
R/W
R/W
R/W
Overflow interrupt enable 2 to 0
These bits enable or disable interrupts by the OVF flags
3
2
OVF2
0
1
R/(W)*
Overflow flags 2 to 0
Status flags indicating overflow
or underflow
Reserved bit
1
0
OVF1
OVF0
0
0
R/(W)*
R/(W)*
(Initial value)
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