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Section 19 Clock Pulse Generator
External Clock: The external clock frequency should be equal to the system clock frequency
when not divided by the on-chip frequency divider. Table 19.3 shows the clock timing, figure 19.6
shows the external clock input timing, and figure 19.7 shows the external clock output settling
delay timing. When the appropriate external clock is input via the EXTAL pin, its waveform is
corrected by the on-chip oscillator and duty adjustment circuit.
When the appropriate external clock is input via the EXTAL pin, its waveform is corrected by the
on-chip oscillator and duty adjustment circuit. The resulting stable clock is output to external
devices after the external clock settling time (t
must remain reset with the reset signal low during t
Table 19.3 Clock Timing
Item
Symbol Min
External clock input
t
low pulse width
External clock input
t
high pulse width
External clock rise
t
time
External clock fall
t
time
Clock low pulse
t
width
Clock high pulse
t
width
External clock
t
output settling
delay time
Notes: 1. t
includes RES pulse width (t
DEXT
t
is 10 tcyc in the mask ROM version, and 20 tcyc in the flash memory and flash
RESW
memory R versions.
2. The operating range "V
Rev. 4.00 Jan 26, 2006 page 670 of 938
REJ09B0276-0400
V
= 2.7 V
CC
to 5.5 V *
2
Max
40
EXL
40
EXH
10
EXr
10
EXf
0.4
0.6
CL
80
0.4
0.6
CH
80
*
1
500
DEXT
= 2.7 V to 5.5 V" applies to the mask ROM version.
CC
) has passed after the clock input. The system
DEXT
, while the clock output is unstable.
DEXT
V
= 3.0 V
V
= 5.0 V ±
CC
CC
to 5.5 V
10%
Min
Max
Min
30
15
30
15
8
8
0.4
0.6
0.4
80
80
0.4
0.6
0.4
80
80
500
500
).
RESW
Max
Unit Test Conditions
ns
Figure 19.6
ns
5
ns
5
ns
φ ≥ 5 MHz
0.6
t
cyc
φ < 5 MHz
ns
φ ≥ 5 MHz
0.6
t
cyc
φ < 5 MHz
ns
µs
Figure 19.7
Figure
21.11
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