Block Diagram - Renesas H8/3067 Series User Manual

Renesas 16-bit single-chip microcomputer
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Section 19 Clock Pulse Generator
19.1.1

Block Diagram

Figure 19.1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL
Figure 19.1 Block Diagram of Clock Pulse Generator
Rev. 4.00 Jan 26, 2006 page 666 of 938
REJ09B0276-0400
Duty
Oscillator
adjustment
circuit
CPG
φ
Frequency
Prescalers
divider
Division
control
register
Data bus
φ pin
φ/2 to φ/4096

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H8/3067H8/3066H8/3065H8/3067rf

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