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Section 21 Electrical Characteristics
T
1
φ
t
AD
A
to A
23
3
CSn
A
to A
2
0
t
ASD
AS
t
AS1
t
ASD
RD
t
AS1
D
to D
15
0
Note:
Specification from the earliest negation timing of A
*
Figure 21.15 Burst ROM Access Timing: Three-State Access
φ
t
BRQS
BREQ
BACK
A
to A
,
23
0
AS, RD,
HWR, LWR
Rev. 4.00 Jan 26, 2006 page 744 of 938
REJ09B0276-0400
T
T
2
3
t
t
ACC4
SD
t
ACC4
t
t
ACC2
RDS
t
BACD1
Figure 21.16 Bus-Release Mode Timing
T
1
t
AD
t
t
ASD
AH
t
AS1
t
ACC2
to A
, CSn, and RD.
23
0
t
BRQS
t
BZD
T
T
2
3
t
t
SD
AH
t
RDS
t
BACD2
t
BZD
t
RSD
*
t
RDH
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