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output, set these bits to 01. Clock output is not performed when the GM bit is set to 1 in SMR.
Clock output can also be fixed low or high.
Smart Card Mode Register (SCMR) Settings: Clear both the SDIR bit and SINV bit cleared to
0 if the smart card is of the direct convention type, and set both to 1 if of the inverse convention
type. To use the smart card interface, set the SMIF bit to 1.
The register settings and examples of starting character waveforms are shown below for two smart
cards, one following the direct convention and one the inverse convention.
1. Direct Convention (SDIR = SINV = O/E = 0)
(Z)
A
Ds
D0
With the direct convention type, the logic 0 level corresponds to state Z and the logic 1 level to
state A, and transfer is performed in LSB-first order. In the example above, the first character
data is H'3B. The parity bit is 1, following the even parity rule designated for smart cards.
2. Indirect Convention (SDIR = SINV = O/E = 1)
(Z)
A
Ds
D7
With the indirect convention type, the logic 1 level corresponds to state Z and the logic 0 level
to state A, and transfer is performed in MSB-first order. In the example above, the first
character data is H'3F. The parity bit is 0, corresponding to state Z, following the even parity
rule designated for smart cards.
In the H8/3067 Group, inversion specified by the SINV bit applies only to the data bits, D7 to
D0. For parity bit inversion, the O/E bit in SMR must be set to odd parity mode. This applies
to both transmission and reception.
Z
Z
A
Z
D1
D2
D3
Z
Z
A
A
D6
D5
D4
Section 14 Smart Card Interface
Z
Z
A
A
D4
D5
D6
D7
A
A
A
A
D3
D2
D1
D0
Rev. 4.00 Jan 26, 2006 page 555 of 938
Z
(Z)
State
Dp
Z
(Z)
State
Dp
REJ09B0276-0400
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